Cadence and TSMC Expand Collaboration for AI and HPC Design
Cadence and TSMC as part of the expanded partnership, Cadence has achieved tool certification for TSMC’s advanced A14 process, demonstrated a UALink solution on TSMC N3P technology and introduced new silicon-proven IP for N3P and N2P processes. The companies are also enabling AI-driven and agentic AI chip design flows across TSMC’s N3, N2, A16™ and A14 technologies.
The collaboration extends to TSMC 3DFabric® technologies, supporting advanced wafer-scale systems that can integrate hundreds of chiplets. These capabilities are designed to help semiconductor companies address increasing demands for performance, energy efficiency and scalability in AI and HPC systems.
Accelerating Advanced Semiconductor Design
Cadence and TSMC have continued to expand their collaboration to help semiconductor designers address the growing complexity of modern chip and system development.
Chin-Chi Teng, senior vice president and general manager of the Digital and Signoff Group at Cadence, said the partnership is focused on enabling customers to accelerate advanced semiconductor designs through AI-driven design flows, silicon-proven IP and 3D-IC solutions.
TSMC is also working with its Open Innovation Platform® (OIP) ecosystem partners to address the performance and energy-efficiency requirements of AI systems. According to Aveek Sarkar, director of the Ecosystem and Alliance Management Division at TSMC, the collaboration with Cadence is helping customers advance AI-based semiconductor development and deliver increasingly capable silicon.
Certified A14 Design Flows for Next-Generation Computing
Cadence has achieved certification for its digital full-flow, signoff and custom/analog design solutions for TSMC’s A16™ and A14 process technologies.
The digital design flow includes the Cadence Innovus™ Implementation System and Cadence Cerebrus® Intelligent Chip Explorer, supporting implementation optimization and design-technology co-optimization. The flow also incorporates advanced signoff technologies, including the Tempus™ Timing and ECO Solution, EMX® Planar 3D Solver, Voltus™ IC Power Integrity Solution, Quantus™ Extraction Solution, Pegasus™ Verification System and Liberate™ Characterization Portfolio, along with the Genus™ Synthesis Solution.
For custom and analog designs, Virtuoso® Studio solutions provide design-rule-correct layout generation and automated design migration for TSMC A16 and A14 technologies. Cadence says these capabilities can reduce design iterations by up to 2.5 times while supporting improved first-pass success for AI, HPC and mobile system-on-chip designs.
The companies are also expanding IP availability for advanced computing applications. UCIe™-64G has taped out on TSMC A14, while LPDDR6 IP is in development. Additional memory and interface IP for compute chiplets is also being prioritized. Artisan® Foundation IP and mixed-signal IP for TSMC A14—including standard cells, GPIO and memory compilers—are in development and are expected to become available in the fourth quarter of 2026.
N2P Design Flows and IP for AI Applications
Cadence has also certified its analog, digital and signoff tool flows for TSMC’s N2P process technology.
The Virtuoso Layout Suite now includes enhanced connectivity models designed to provide a production-ready custom design environment and enable faster design starts. The certified flows are intended to support improved designer productivity and accelerate tape-outs.
Cadence has already taped out several IP blocks on N2P, including DDR5, LPDDR5 and PCIe 6.0. PCIe 3.0 IP is expected to tape out in the fourth quarter of 2026. UCIe-64G IP implemented on N2P silicon is currently undergoing laboratory testing, while the technology has also been characterized on N3P.
These capabilities are designed to support infrastructure AI, Physical AI and other demanding compute applications that require high-performance memory and interconnect technologies.
Scaling 3D-IC Systems to Hundreds of Chiplets
As AI and HPC systems become increasingly complex, advanced packaging and chiplet-based architectures are becoming critical to achieving greater compute performance and scalability.
It solutions are enabled to support TSMC’s SoW-X full design flow, including systems incorporating hundreds of chiplets and millions of bumps. Cadence also supports the design of advanced packages up to five times reticle size using CoWoS-L-style architectures.
The company’s Integrity 3D-IC solution enables designers to integrate key technologies—including SoIC, eDTC, MIMCap, IVR, HBM logic base die and substrates—within advanced system architectures.
It has also introduced a pre-simulation-driven die-to-die auto-routing flow certified with the Cadence Allegro® Substrate Router and Cadence OmniRoute Advanced Interconnect Router. The technology can automatically derive signal-integrity-optimized routing strategies across CoWoS® architectures while targeting UCIe requirements.
Supporting High-Bandwidth Connectivity
The collaboration also extends to TSMC-COUPE™, or Compact Universal Photonic Engine, which supports high-bandwidth photonic-to-silicon connectivity and is enabled for integration with Cadence 224G SerDes IP.
The SerDes technology is aligned with emerging connectivity ecosystems including UALink, ESUN, Ultra Ethernet and co-packaged optics (CPO). It complements It’s broader portfolio of AI and HPC IP, which includes HBM4/4E, LPDDR6/5X, DDR5-MRDIMM, PCIe 7.0 and UCIe 64G.
Together, these technologies are designed to address the increasing bandwidth, memory and interconnect requirements of next-generation AI infrastructure.
Global Unichip Advances Leading-Edge Designs
Global Unichip Corp. (GUC) is using Cadence solutions to develop advanced custom silicon for AI accelerators and hyperscale computing systems based on TSMC’s leading-edge process technologies.
According to Louis Lin, senior vice president at GUC, increasingly complex designs on technologies such as N3P and N2P require highly optimized execution and predictable design flows. Cadence solutions are helping GUC manage schedule risks and support complex designs through tape-out.
Cadence and TSMC to Showcase Innovations at 2026 OIP Forum
The latest innovations resulting from the Cadence-TSMC collaboration will be showcased at the 2026 TSMC North America OIP Ecosystem Forum, held September 23 at the Santa Clara Convention Center.
The event will highlight the companies’ latest work in AI-driven semiconductor design, advanced process technologies, chiplet architectures, 3D-IC integration and silicon-proven IP.
About Cadence
It (Nasdaq: CDNS) is a technology company focused on computational software and AI-driven solutions for engineering design, from semiconductor chips to complete systems. Through its Intelligent System Design™ strategy, Cadence provides design technologies used by semiconductor and systems companies across markets including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics.
Founded on decades of semiconductor design expertise, Cadence develops solutions that help customers address increasingly complex engineering challenges and accelerate the development of next-generation products.
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