Cadence today unveiled a broad set of breakthroughs in electronic design automation (EDA), intellectual property (IP), and advanced chip design methodologies. These advancements stem from its deep, long-term collaboration with TSMC, a partnership that continues to push the boundaries of semiconductor innovation for next-generation AI and high-performance computing (HPC) markets. By aligning closely on process development, design flows, and advanced integration technologies, Cadence and TSMC are enabling customers worldwide to accelerate time to market while building increasingly sophisticated silicon solutions.
Strengthening a Strategic Collaboration
For more than a decade, Cadence and TSMC have collaborated across a wide spectrum of technologies—from traditional EDA and system analysis to cutting-edge 3D-IC design, silicon-proven IP, and emerging photonics capabilities. This partnership ensures that each new generation of TSMC’s advanced process technologies is supported by robust Cadence tools, AI-enhanced flows, and validated methodologies. Together, the companies are enabling the rapid development of the world’s most advanced semiconductor devices.
Cadence’s latest advancements reflect significant joint efforts with TSMC on advanced design ecosystems for the N3, N2, and forthcoming A16™ process nodes. These efforts leverage Cadence’s comprehensive suite of digital, custom, and analog tools—including the Innovus™ Implementation System, Tempus™ Timing Solution, Quantus™ Extraction Solution with Field Solver technology, Pegasus™ Verification System, Liberate™ Characterization Portfolio, Genus™ Synthesis Solution, Virtuoso® Studio, and the Spectre® Simulation Platform. The two companies have also worked closely on developing power integrity, thermal analysis, and system-level verification flows using platforms such as Voltus™, Clarity™, and Sigrity™ X.
These tools now fully support TSMC’s newest process offerings, including breakthrough enhancements in 3DFabric™ technologies for advanced packaging and die stacking. Additionally, Cadence has begun collaborating on design enablement flows for TSMC’s A14 process node, with the initial process design kit (PDK) expected to become available later this year. Alongside design automation support, Cadence announced that several new pieces of IP have reached silicon-proven status on TSMC’s N3P process, making them immediately available to customers.
Executive Perspectives on Accelerating the Future of AI and HPC
Chin-Chi Teng, senior vice president and general manager of the Digital and Signoff Group at Cadence, emphasized the shared mission between the two companies: “Cadence and TSMC remain committed to accelerating and improving the design process for advanced silicon,” he said. “Through our AI-enhanced technologies, leading-edge IP, and deep integration with TSMC’s most advanced nodes, we are enabling customers to build the next generation of AI and HPC systems more efficiently.”
TSMC echoed this sentiment. Aveek Sarkar, director of the Ecosystem and Alliance Management Division, highlighted the importance of the Open Innovation Platform® (OIP) ecosystem: “Together with partners like Cadence, we are addressing the most complex technological challenges in modern semiconductor development. This collaboration is essential to achieving greater performance and energy efficiency in AI systems,” Sarkar stated. “Our long-standing partnership continues to empower customers to accelerate their path to silicon and support the rapid and wide-reaching expansion of AI applications.”
AI-Driven Design for TSMC’s Most Advanced Processes
One of the most impactful areas of collaboration is the integration of AI into chip design workflows. As chip architectures become more intricate—particularly for AI accelerators, HPC processors, and multi-die systems—the demand for automated, intelligent design optimization has surged.
Cadence and TSMC have jointly enhanced AI-driven design flows for the N2 node, enabling customers to achieve optimal power, performance, and area (PPA) at a fraction of the traditional design effort. Central to this collaboration is the Cadence JedAI platform, which unifies massive design datasets and provides machine-learning-driven analytics, and Cadence Cerebrus®, the AI-powered implementation and optimization engine.
TSMC has validated key features from these platforms—including new AI assistants integrated directly into Innovus+. These capabilities automate tasks such as design rule check (DRC) violation resolution and layout optimization, significantly improving engineering productivity while accelerating design closure. As a result, semiconductor teams can more easily meet the stringent architectural and performance requirements of advanced AI chips targeting the N2 node.
Boosting Efficiency and Scalability in 3D-IC Design
As the entire semiconductor industry shifts toward heterogeneous integration, multi-die systems, and advanced packaging, Cadence and TSMC have worked together to create robust design flows for 3DFabric™ technologies. These advancements are essential for companies building large AI accelerators, memory-rich compute subsystems, and chiplet-based architectures.
Cadence’s 3D-IC suite now delivers full end-to-end support for TSMC’s die stacking solutions. Key new innovations include:
- Automated bump and redistribution layer management
- Cross-die physical implementation and analysis for multi-chiplet systems
- Automated alignment marker insertion for precise die stacking
- AI-driven electromagnetic and signal/power integrity modeling using Clarity™, Sigrity™ X, and Optimality™
In addition, customers working with TSMC’s Compact Universal Photonic Engine (TSMC-COUPE™) can take advantage of specialized flows using Virtuoso Studio combined with the Celsius™ Thermal Solver. These solutions incorporate advanced thermal simulation capabilities—developed collaboratively by TSMC and Cadence—to mitigate thermal-induced performance degradation in both electronic and photonic components.
Silicon-Proven IP on TSMC N3P for AI and HPC Workloads
Cadence is also expanding its IP portfolio for next-generation AI and HPC systems, with a particular focus on high-bandwidth memory, advanced interconnects, and high-speed interfaces required for large-scale AI workloads.
Several significant IP announcements include:
- The industry’s first HBM4 IP on TSMC’s N3P process, enabling massive memory bandwidth for AI training systems
- New LPDDR6/5X controller and PHY solutions operating at 14.4Gbps
- Next-generation DDR5 MRDIMM Gen2 IP at 12.8Gbps to help overcome the “memory wall”
- PCIe® 7.0 IP achieving 128GT/s performance, ready for next-generation data center architectures
- 224G SerDes optimized for AI infrastructure interconnects
- The industry’s first eUSB2V2 and UCIe™ 32G IPs for emerging chiplet-based ecosystems
These IP solutions provide scalable, energy-efficient building blocks for AI infrastructure—ranging from agentic AI applications and LLMs to edge AI PCs and advanced chiplet-based compute architectures.
Enabling the AI Supercycle
Through the combined strength of Cadence, TSMC, and the broader OIP ecosystem, customers now have access to an advanced collection of tools, IP, and validated flows that streamline the entire journey from initial design exploration to tape-out and silicon manufacturing. This collaboration supports the accelerating demand for AI computing, enabling companies to create systems that offer superior performance, energy efficiency, and scalability.
Source Link:https://www.cadence.com/
