Cadence Launches Industry-First 14.4Gbps LPDDR6/5X Memory IP to Accelerate AI Infrastructure
Cadence has announced the successful tapeout of the industry’s first LPDDR6/5X memory IP system solution optimized to operate at 14.4Gbps, marking a significant leap in memory performance. The new solution delivers up to 50% higher data rates compared to the previous LPDDR generation and is specifically engineered to meet the growing demands of next-generation artificial intelligence (AI) infrastructure.
As the computing landscape undergoes a transformative shift toward AI-driven workloads—including large language models (LLMs), agentic AI systems, and data-intensive compute tasks across diverse verticals—the need for faster and more efficient memory has never been more critical. With multiple engagements already underway with leading companies in AI, high-performance computing (HPC), and cloud data centers, Cadence’s new memory IP solution is poised to be a foundational element in the next wave of AI scalability.
The LPDDR6/5X memory IP system solution from Cadence includes both a high-performance controller and an advanced physical interface (PHY) that support the latest JEDEC LPDDR6 and LPDDR5X DRAM standards. This system-level solution delivers a comprehensive architecture designed to optimize power, performance, and area (PPA), making it highly suitable for a broad spectrum of markets—including AI accelerators, mobile devices, consumer electronics, enterprise HPC, and cloud infrastructure.
A notable feature of the Cadence solution is its adaptability. It supports integration into traditional monolithic SoCs as well as multi-die, chiplet-based systems. By leveraging the Cadence chiplet framework, which has already been proven in silicon with the previous generation of LPDDR memory, customers can take advantage of heterogeneous chiplet integration to optimize design flexibility, power efficiency, and time-to-market. The 2024 tapeout of this framework demonstrated its viability for production-ready solutions in leading-edge applications.
“As data centers continue their evolution—from traditional HPC virtualization to large-scale AI training and inference—the memory subsystem has become a critical factor in performance and efficiency,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. “LPDDR6 is a key enabler for accelerated AI compute, offering the speed, bandwidth, and energy efficiency necessary to meet the demands of modern workloads. This tapeout reaffirms Cadence’s leadership in memory IP innovation by delivering an integrated LPDDR6 subsystem ready for deployment.”
Cadence’s LPDDR6/5X memory system is built on the company’s proven design heritage, which includes successful implementations of DDR5 at 12.8Gbps, LPDDR5X at 10.7Gbps, and GDDR7 up to 36Gbps. This LPDDR6 solution represents the first product in a new line of LPDDR6 IP offerings and is fully compliant with both LPDDR6 and LPDDR5X specifications, including support for the emerging LPDDR5X CAMM2 module format.
Designed for maximum flexibility, the LPDDR6/5X PHY is available as a hardened, drop-in macro that can be customized to accommodate various packaging and system topologies. This allows for rapid, reliable integration into customer designs, significantly reducing development cycles and accelerating time to market.
The accompanying memory controller is delivered as a soft RTL macro, allowing customers to tailor the implementation to their specific needs in terms of power, area, and features. It includes a full range of industry-standard capabilities, such as support for the Arm® AMBA® AXI bus interface, along with advanced memory interface features designed to maximize performance and compatibility.
To support design verification and standard compliance, the LPDDR6/5X solution includes the Cadence LPDDR6 Memory Model. This model enables engineers to verify system-on-chip (SoC) compatibility with the latest JEDEC standards through comprehensive protocol checking, functional coverage, and a robust verification plan. This ensures that customers can confidently adopt the LPDDR6 technology in their designs.
The new LPDDR6/5X IP is now available for customer engagements and joins Cadence’s expansive portfolio of memory interface IP, which includes solutions for DDR, GDDR, and HBM. All Cadence memory IP is developed using the company’s world-class analog and mixed-signal design tools, ensuring industry-leading quality and reliability.
When combined with Cadence’s UCIe™-based chiplet integration framework, the LPDDR6/5X IP solution enables an optimized path for chiplet-based designs in cutting-edge applications.