At Cadence, we’re dedicated to nurturing the next generation of innovators. Our commitment to education and innovation drives us to eliminate barriers that prevent academia and entrepreneurs from accessing the commercial-grade tools and technologies essential to advancing semiconductor design.
When the academic community and early-stage startups lost access to a multi-project wafer (MPW) aggregation service, threatening to stall their work, Cadence partnered with SkyWater Technology to deliver a new solution based on the SKY130 open-source process — ensuring that innovation continues to thrive.
“To prepare the next generation of engineers, we need to give them practical experience bringing ideas from concept to tapeout,” said David Junkin, Academic Network Program Manager at Cadence. “By partnering with SkyWater, we’ve created a way for academia and early-stage startups to do exactly that — using commercial-grade tools to turn their designs into real silicon.”
Removing Barriers to Real Silicon Experience
The Cadence MPW aggregation service allows engineers to design using any commercial or open-source EDA tool and implement designs on the SKY130 process. Because SKY130 is open source, no NDA is required, removing a common barrier that limits student and startup participation.
The first shuttle successfully supported multiple academic and startup projects, helping several students complete their first-ever tapeouts and enabling emerging companies to move forward in critical funding stages.
“At SkyWater, we recognize the importance of expanding access to advanced semiconductor manufacturing,” said Percy Gilbert, SVP of Engineering at SkyWater Technology. “By collaborating with Cadence to provide MPW access on our SKY130 process, we’re giving students, researchers, and entrepreneurs a reliable, manufacturable platform for true tapeout experience — strengthening the future talent pipeline and demonstrating how U.S.-based manufacturing can accelerate innovation.”
Real-World Impact in the Classroom and Beyond
Across universities, professors and students are integrating SKY130 into their courses and research — combining open access with commercial-grade design tools to create a powerful hands-on learning environment.
At Georgia Tech, the SiliconJackets student team gained real-world insights by taping out a six-stage single-core RISC-V CPU.
“The Cadence MPW allowed us to understand real-world design constraints and refine our skills with industry-standard tools,” said Zachary Ellis, Co-Founder and Former President of SiliconJackets.
At North Carolina State University, students designed and taped out a mixed-signal NFC tag with a Rocket Chip RISC-V processor as part of a new industry-style course.
“The SKY130 PDK is a truly open platform that elevates the educational experience,” said W. Shepherd Pitts, PhD, Professor of ECE at NC State. “Students aren’t just learning flows — they’re contributing to a living ecosystem of open-source innovation.”
At UC Berkeley, students in the EECS151 Tapeout course designed two RISC-V SoCs using the open SKY130 process, supported by Cadence and SkyWater.
“Cadence responded quickly to help us adapt to the new shuttle and provided the tools and support we needed,” said Jim Fang, Elam Day-Friedland, and Lucy Revina, representing the Berkeley team. “This openness lets us share flows, publish our curriculum, and contribute back to the broader open silicon community.”
Next Shuttle Now Open
Cadence is now accepting submissions for the next MPW shuttle, open through January 16, 2026. By combining open access with industry-grade tools, the program continues to empower students, educators, researchers, and entrepreneurs to bring their ideas to life in silicon — helping shape the future of semiconductor innovation.
